# SAM4S HSMCI

## High Speed MultiMedia Card Interface (HSMCI) User Interface

### Registers

Register Mapping
Address | Register | Name | Access | Reset
--- | --- | --- | --- | ---
0x40000000 | Control Register | HSMCI_CR | write-only | -
0x40000004 | Mode Register | HSMCI_MR | read-write | 0x00000000
0x40000008 | Data Timeout Register | HSMCI_DTOR | read-write | 0x00000000
0x4000000C | SD/SDIO Card Register | HSMCI_SDCR | read-write | 0x00000000
0x40000010 | Argument Register | HSMCI_ARGR | read-write | 0x00000000
0x40000014 | Command Register | HSMCI_CMDR | write-only | -
0x40000018 | Block Register | HSMCI_BLKR | read-write | 0x00000000
0x4000001C | Completion Signal Timeout Register | HSMCI_CSTOR | read-write | 0x00000000
0x40000020 | Response Register | HSMCI_RSPR[4] | read-only | 0x00000000
0x40000030 | Receive Data Register | HSMCI_RDR | read-only | 0x00000000
0x40000034 | Transmit Data Register | HSMCI_TDR | write-only | -
0x40000040 | Status Register | HSMCI_SR | read-only | 0x0000C0E5
0x40000044 | Interrupt Enable Register | HSMCI_IER | write-only | -
0x40000048 | Interrupt Disable Register | HSMCI_IDR | write-only | -
0x4000004C | Interrupt Mask Register | HSMCI_IMR | read-only | 0x00000000
0x40000054 | Configuration Register | HSMCI_CFG | read-write | 0x00000000
0x400000E4 | Write Protection Mode Register | HSMCI_WPMR | read-write | -
0x400000E8 | Write Protection Status Register | HSMCI_WPSR | read-only | -
0x40000200 | FIFO Memory Aperture0 | HSMCI_FIFO[256] | read-write | 0x0
0x40000100 | Receive Pointer Register | HSMCI_RPR | read-write | 0x00000000
0x40000104 | Receive Counter Register | HSMCI_RCR | read-write | 0x00000000
0x40000108 | Transmit Pointer Register | HSMCI_TPR | read-write | 0x00000000
0x4000010C | Transmit Counter Register | HSMCI_TCR | read-write | 0x00000000
0x40000110 | Receive Next Pointer Register | HSMCI_RNPR | read-write | 0x00000000
0x40000114 | Receive Next Counter Register | HSMCI_RNCR | read-write | 0x00000000
0x40000118 | Transmit Next Pointer Register | HSMCI_TNPR | read-write | 0x00000000
0x4000011C | Transmit Next Counter Register | HSMCI_TNCR | read-write | 0x00000000
0x40000120 | Transfer Control Register | HSMCI_PTCR | write-only | 0x00000000
0x40000124 | Transfer Status Register | HSMCI_PTSR | read-only | 0x00000000

### Register Fields

#### HSMCI Control Register

Name: HSMCI_CR

Access: write-only

Address: 0x40000000

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SWRST | - | - | - | PWSDIS | PWSEN | MCIDIS | MCIEN

- MCIEN: Multi-Media Interface Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the Multi-Media Interface if MCDIS is 0.

- MCIDIS: Multi-Media Interface Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the Multi-Media Interface.

- PWSEN: Power Save Mode Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the Power Saving Mode if PWSDIS is 0.

- PWSDIS: Power Save Mode Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the Power Saving Mode.

- SWRST: Software Reset

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Resets the HSMCI. A software triggered hardware reset of the HSMCI interface is performed.

#### HSMCI Mode Register

Name: HSMCI_MR

Access: read-write

Address: 0x40000004

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
PDCMODE | PADV | FBYTE | WRPROOF | RDPROOF | PWSDIV
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CLKDIV

- CLKDIV: Clock Divider

-

- PWSDIV: Power Saving Divider

-

- RDPROOF

  Value | Name | Description
  --- | --- | ---
  0 | - | Disables Read Proof.
  1 | - | Enables Read Proof.

- WRPROOF

  Value | Name | Description
  --- | --- | ---
  0 | - | Disables Write Proof.
  1 | - | Enables Write Proof.

- FBYTE: Force Byte Transfer

  Value | Name | Description
  --- | --- | ---
  0 | - | Disables Force Byte Transfer.
  1 | - | Enables Force Byte Transfer.

- PADV: Padding Value

  Value | Name | Description
  --- | --- | ---
  0 | - | 0x00 value is used when padding data in write transfer.
  1 | - | 0xFF value is used when padding data in write transfer.

- PDCMODE: PDC-oriented Mode

  Value | Name | Description
  --- | --- | ---
  0 | - | Disables PDC transfer
  1 | - | Enables PDC transfer. In this case, UNRE and OVRE flags in the MCI Mode Register (MCI_SR) are deactivated after the PDC transfer has been completed.

#### HSMCI Data Timeout Register

Name: HSMCI_DTOR

Access: read-write

Address: 0x40000008

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | DTOMUL | DTOCYC

- DTOCYC: Data Timeout Cycle Number

-

- DTOMUL: Data Timeout Multiplier

  Value | Name | Description
  --- | --- | ---
  0x0 | 1 | DTOCYC
  0x1 | 16 | DTOCYC x 16
  0x2 | 128 | DTOCYC x 128
  0x3 | 256 | DTOCYC x 256
  0x4 | 1024 | DTOCYC x 1024
  0x5 | 4096 | DTOCYC x 4096
  0x6 | 65536 | DTOCYC x 65536
  0x7 | 1048576 | DTOCYC x 1048576

#### HSMCI SD/SDIO Card Register

Name: HSMCI_SDCR

Access: read-write

Address: 0x4000000C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SDCBUS | - | - | - | - | SDCSEL

- SDCSEL: SDCard/SDIO Slot

  Value | Name | Description
  --- | --- | ---
  0x0 | SLOTA | Slot A is selected.
  0x1 | SLOTB | -
  0x2 | SLOTC | -
  0x3 | SLOTD | -

- SDCBUS: SDCard/SDIO Bus Width

  Value | Name | Description
  --- | --- | ---
  0x0 | 1 | 1 bit
  0x2 | 4 | 4 bit
  0x3 | 8 | 8 bit

#### HSMCI Argument Register

Name: HSMCI_ARGR

Access: read-write

Address: 0x40000010

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
ARG
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ARG
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
ARG
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ARG

- ARG: Command Argument

-

#### HSMCI Command Register

Name: HSMCI_CMDR

Access: write-only

Address: 0x40000014

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | BOOT_ACK | ATACS | IOSPCMD
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | TRTYP | TRDIR | TRCMD
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | MAXLAT | OPDCMD | SPCMD
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RSPTYP | CMDNB

- CMDNB: Command Number

-

- RSPTYP: Response Type

  Value | Name | Description
  --- | --- | ---
  0x0 | NORESP | No response.
  0x1 | 48_BIT | 48-bit response.
  0x2 | 136_BIT | 136-bit response.
  0x3 | R1B | R1b response type

- SPCMD: Special Command

  Value | Name | Description
  --- | --- | ---
  0x0 | STD | Not a special CMD.
  0x1 | INIT | Initialization CMD: 74 clock cycles for initialization sequence.
  0x2 | SYNC | Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command.
  0x3 | CE_ATA | CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line.
  0x4 | IT_CMD | Interrupt command: Corresponds to the Interrupt Mode (CMD40).
  0x5 | IT_RESP | Interrupt response: Corresponds to the Interrupt Mode (CMD40).
  0x6 | BOR | Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly.
  0x7 | EBO | End Boot Operation. This command allows the host processor to terminate the boot operation mode.

- OPDCMD: Open Drain Command

  Value | Name | Description
  --- | --- | ---
  0 | PUSHPULL | Push pull command.
  1 | OPENDRAIN | Open drain command.

- MAXLAT: Max Latency for Command to Response

  Value | Name | Description
  --- | --- | ---
  0 | 5 | 5-cycle max latency.
  1 | 64 | 64-cycle max latency.

- TRCMD: Transfer Command

  Value | Name | Description
  --- | --- | ---
  0x0 | NO_DATA | No data transfer
  0x1 | START_DATA | Start data transfer
  0x2 | STOP_DATA | Stop data transfer

- TRDIR: Transfer Direction

  Value | Name | Description
  --- | --- | ---
  0 | WRITE | Write.
  1 | READ | Read.

- TRTYP: Transfer Type

  Value | Name | Description
  --- | --- | ---
  0x0 | SINGLE | MMC/SDCard Single Block
  0x1 | MULTIPLE | MMC/SDCard Multiple Block
  0x2 | STREAM | MMC Stream
  0x4 | BYTE | SDIO Byte
  0x5 | BLOCK | SDIO Block

- IOSPCMD: SDIO Special Command

  Value | Name | Description
  --- | --- | ---
  0x0 | STD | Not an SDIO Special Command
  0x1 | SUSPEND | SDIO Suspend Command
  0x2 | RESUME | SDIO Resume Command

- ATACS: ATA with Command Completion Signal

  Value | Name | Description
  --- | --- | ---
  0 | NORMAL | Normal operation mode.
  1 | COMPLETION | This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR).

- BOOT_ACK: Boot Operation Acknowledge.

-

#### HSMCI Block Register

Name: HSMCI_BLKR

Access: read-write

Address: 0x40000018

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BLKLEN
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BLKLEN
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
BCNT
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
BCNT

- BCNT: MMC/SDIO Block Count - SDIO Byte Count

  Value | Name | Description
  --- | --- | ---
  0x0 | MULTIPLE | MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer.
  0x4 | BYTE | SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden.
  0x5 | BLOCK | SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden.

- BLKLEN: Data Block Length

-

#### HSMCI Completion Signal Timeout Register

Name: HSMCI_CSTOR

Access: read-write

Address: 0x4000001C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | CSTOMUL | CSTOCYC

- CSTOCYC: Completion Signal Timeout Cycle Number

-

- CSTOMUL: Completion Signal Timeout Multiplier

  Value | Name | Description
  --- | --- | ---
  0x0 | 1 | CSTOCYC x 1
  0x1 | 16 | CSTOCYC x 16
  0x2 | 128 | CSTOCYC x 128
  0x3 | 256 | CSTOCYC x 256
  0x4 | 1024 | CSTOCYC x 1024
  0x5 | 4096 | CSTOCYC x 4096
  0x6 | 65536 | CSTOCYC x 65536
  0x7 | 1048576 | CSTOCYC x 1048576

#### HSMCI Response Register

Name: HSMCI_RSPR[0:3]

Access: read-only

Address: 0x40000020

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RSP
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RSP
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RSP
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RSP

- RSP: Response

-

#### HSMCI Receive Data Register

Name: HSMCI_RDR

Access: read-only

Address: 0x40000030

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
DATA
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
DATA
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
DATA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
DATA

- DATA: Data to Read

-

#### HSMCI Transmit Data Register

Name: HSMCI_TDR

Access: write-only

Address: 0x40000034

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
DATA
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
DATA
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
DATA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
DATA

- DATA: Data to Write

-

#### HSMCI Status Register

Name: HSMCI_SR

Access: read-only

Address: 0x40000040

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
UNRE | OVRE | ACKRCVE | ACKRCV | XFRDONE | FIFOEMPTY | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CSTOE | DTOE | DCRCE | RTOE | RENDE | RCRCE | RDIRE | RINDE
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TXBUFE | RXBUFF | CSRCV | SDIOWAIT | - | - | - | SDIOIRQA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ENDTX | ENDRX | NOTBUSY | DTIP | BLKE | TXRDY | RXRDY | CMDRDY

- CMDRDY: Command Ready

  Value | Name | Description
  --- | --- | ---
  0 | - | A command is in progress.
  1 | - | The last command has been sent. Cleared when writing in the HSMCI_CMDR.

- RXRDY: Receiver Ready

  Value | Name | Description
  --- | --- | ---
  0 | - | Data has not yet been received since the last read of HSMCI_RDR.
  1 | - | Data has been received since the last read of HSMCI_RDR.

- TXRDY: Transmit Ready

  Value | Name | Description
  --- | --- | ---
  0 | - | The last data written in HSMCI_TDR has not yet been transferred in the Shift Register.
  1 | - | The last data written in HSMCI_TDR has been transferred in the Shift Register.

- BLKE: Data Block Ended

  Value | Name | Description
  --- | --- | ---
  0 | - | A data block transfer is not yet finished. Cleared when reading the HSMCI_SR.
  1 | - | A data block transfer has ended, including the CRC16 Status transmission. the flag is set for each transmitted CRC Status.

- DTIP: Data Transfer in Progress

  Value | Name | Description
  --- | --- | ---
  0 | - | No data transfer in progress.
  1 | - | The current data transfer is still in progress, including CRC16 calculation. Cleared at the end of the CRC16 calculation.

- NOTBUSY: HSMCI Not Busy

  Value | Name | Description
  --- | --- | ---
  0 | - | The HSMCI is not ready for new data transfer. Cleared at the end of the card response.
  1 | - | The HSMCI is ready for new data transfer. Set when the busy state on the data line has ended. This corresponds to a free internal data receive buffer of the card.

- ENDRX: End of RX Buffer

  Value | Name | Description
  --- | --- | ---
  0 | - | The Receive Counter Register has not reached 0 since the last write in HSMCI_RCR or HSMCI_RNCR.
  1 | - | The Receive Counter Register has reached 0 since the last write in HSMCI_RCR or HSMCI_RNCR.

- ENDTX: End of TX Buffer

  Value | Name | Description
  --- | --- | ---
  0 | - | The Transmit Counter Register has not reached 0 since the last write in HSMCI_TCR or HSMCI_TNCR.
  1 | - | The Transmit Counter Register has reached 0 since the last write in HSMCI_TCR or HSMCI_TNCR.

- SDIOIRQA: SDIO Interrupt for Slot A

  Value | Name | Description
  --- | --- | ---
  0 | - | No interrupt detected on SDIO Slot A.
  1 | - | An SDIO Interrupt on Slot A occurred. Cleared when reading the HSMCI_SR.

- SDIOWAIT: SDIO Read Wait Operation Status

  Value | Name | Description
  --- | --- | ---
  0 | - | Normal Bus operation.
  1 | - | The data bus has entered IO wait state.

- CSRCV: CE-ATA Completion Signal Received

  Value | Name | Description
  --- | --- | ---
  0 | - | No completion signal received since last status read operation.
  1 | - | The device has issued a command completion signal on the command line. Cleared by reading in the HSMCI_SR register.

- RXBUFF: RX Buffer Full

  Value | Name | Description
  --- | --- | ---
  0 | - | HSMCI_RCR or HSMCI_RNCR has a value other than 0.
  1 | - | Both HSMCI_RCR and HSMCI_RNCR have a value of 0.

- TXBUFE: TX Buffer Empty

  Value | Name | Description
  --- | --- | ---
  0 | - | HSMCI_TCR or HSMCI_TNCR has a value other than 0.
  1 | - | Both HSMCI_TCR and HSMCI_TNCR have a value of 0.

- RINDE: Response Index Error

  Value | Name | Description
  --- | --- | ---
  0 | - | No error.
  1 | - | A mismatch is detected between the command index sent and the response index received. Cleared when writing in the HSMCI_CMDR.

- RDIRE: Response Direction Error

  Value | Name | Description
  --- | --- | ---
  0 | - | No error.
  1 | - | The direction bit from card to host in the response has not been detected.

- RCRCE: Response CRC Error

  Value | Name | Description
  --- | --- | ---
  0 | - | No error.
  1 | - | A CRC7 error has been detected in the response. Cleared when writing in the HSMCI_CMDR.

- RENDE: Response End Bit Error

  Value | Name | Description
  --- | --- | ---
  0 | - | No error.
  1 | - | The end bit of the response has not been detected. Cleared when writing in the HSMCI_CMDR.

- RTOE: Response Time-out Error

  Value | Name | Description
  --- | --- | ---
  0 | - | No error.
  1 | - | The response time-out set by MAXLAT in the HSMCI_CMDR has been exceeded. Cleared when writing in the HSMCI_CMDR.

- DCRCE: Data CRC Error

  Value | Name | Description
  --- | --- | ---
  0 | - | No error.
  1 | - | A CRC16 error has been detected in the last data block. Cleared by reading in the HSMCI_SR register.

- DTOE: Data Time-out Error

  Value | Name | Description
  --- | --- | ---
  0 | - | No error.
  1 | - | The data time-out set by DTOCYC and DTOMUL in HSMCI_DTOR has been exceeded. Cleared by reading in the HSMCI_SR register.

- CSTOE: Completion Signal Time-out Error

  Value | Name | Description
  --- | --- | ---
  0 | - | No error.
  1 | - | The completion signal time-out set by CSTOCYC and CSTOMUL in HSMCI_CSTOR has been exceeded. Cleared by reading in the HSMCI_SR register. Cleared by reading in the HSMCI_SR register.

- FIFOEMPTY: FIFO empty flag

  Value | Name | Description
  --- | --- | ---
  0 | - | FIFO contains at least one byte.
  1 | - | FIFO is empty.

- XFRDONE: Transfer Done flag

  Value | Name | Description
  --- | --- | ---
  0 | - | A transfer is in progress.
  1 | - | Command register is ready to operate and the data bus is in the idle state.

- ACKRCV: Boot Operation Acknowledge Received

  Value | Name | Description
  --- | --- | ---
  0 | - | No Boot acknowledge received since the last read of the status register.
  1 | - | A Boot acknowledge signal has been received. Cleared by reading the HSMCI_SR register.

- ACKRCVE: Boot Operation Acknowledge Error

  Value | Name | Description
  --- | --- | ---
  0 | - | No error
  1 | - | Corrupted Boot Acknowledge signal received.

- OVRE: Overrun

  Value | Name | Description
  --- | --- | ---
  0 | - | No error.
  1 | - | At least one 8-bit received data has been lost (not read). Cleared when sending a new data transfer command.

- UNRE: Underrun

  Value | Name | Description
  --- | --- | ---
  0 | - | No error.
  1 | - | At least one 8-bit data has been sent without valid information (not written). Cleared when sending a new data transfer command or when setting FERRCTRL in HSMCI_CFG to 1.

#### HSMCI Interrupt Enable Register

Name: HSMCI_IER

Access: write-only

Address: 0x40000044

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
UNRE | OVRE | ACKRCVE | ACKRCV | XFRDONE | FIFOEMPTY | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CSTOE | DTOE | DCRCE | RTOE | RENDE | RCRCE | RDIRE | RINDE
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TXBUFE | RXBUFF | CSRCV | SDIOWAIT | - | - | - | SDIOIRQA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ENDTX | ENDRX | NOTBUSY | DTIP | BLKE | TXRDY | RXRDY | CMDRDY

- CMDRDY: Command Ready Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- RXRDY: Receiver Ready Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- TXRDY: Transmit Ready Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- BLKE: Data Block Ended Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- DTIP: Data Transfer in Progress Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- NOTBUSY: Data Not Busy Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- ENDRX: End of Receive Buffer Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- ENDTX: End of Transmit Buffer Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- SDIOIRQA: SDIO Interrupt for Slot A Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- SDIOWAIT: SDIO Read Wait Operation Status Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- CSRCV: Completion Signal Received Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- RXBUFF: Receive Buffer Full Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- TXBUFE: Transmit Buffer Empty Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- RINDE: Response Index Error Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- RDIRE: Response Direction Error Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- RCRCE: Response CRC Error Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- RENDE: Response End Bit Error Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- RTOE: Response Time-out Error Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- DCRCE: Data CRC Error Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- DTOE: Data Time-out Error Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- CSTOE: Completion Signal Timeout Error Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- FIFOEMPTY: FIFO empty Interrupt enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- XFRDONE: Transfer Done Interrupt enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- ACKRCV: Boot Acknowledge Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- ACKRCVE: Boot Acknowledge Error Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- OVRE: Overrun Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

- UNRE: Underrun Interrupt Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the corresponding interrupt.

#### HSMCI Interrupt Disable Register

Name: HSMCI_IDR

Access: write-only

Address: 0x40000048

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
UNRE | OVRE | ACKRCVE | ACKRCV | XFRDONE | FIFOEMPTY | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CSTOE | DTOE | DCRCE | RTOE | RENDE | RCRCE | RDIRE | RINDE
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TXBUFE | RXBUFF | CSRCV | SDIOWAIT | - | - | - | SDIOIRQA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ENDTX | ENDRX | NOTBUSY | DTIP | BLKE | TXRDY | RXRDY | CMDRDY

- CMDRDY: Command Ready Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- RXRDY: Receiver Ready Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- TXRDY: Transmit Ready Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- BLKE: Data Block Ended Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- DTIP: Data Transfer in Progress Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- NOTBUSY: Data Not Busy Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- ENDRX: End of Receive Buffer Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- ENDTX: End of Transmit Buffer Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- SDIOIRQA: SDIO Interrupt for Slot A Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- SDIOWAIT: SDIO Read Wait Operation Status Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- CSRCV: Completion Signal received interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- RXBUFF: Receive Buffer Full Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- TXBUFE: Transmit Buffer Empty Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- RINDE: Response Index Error Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- RDIRE: Response Direction Error Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- RCRCE: Response CRC Error Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- RENDE: Response End Bit Error Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- RTOE: Response Time-out Error Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- DCRCE: Data CRC Error Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- DTOE: Data Time-out Error Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- CSTOE: Completion Signal Time out Error Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- FIFOEMPTY: FIFO empty Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- XFRDONE: Transfer Done Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- ACKRCV: Boot Acknowledge Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- ACKRCVE: Boot Acknowledge Error Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- OVRE: Overrun Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

- UNRE: Underrun Interrupt Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the corresponding interrupt.

#### HSMCI Interrupt Mask Register

Name: HSMCI_IMR

Access: read-only

Address: 0x4000004C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
UNRE | OVRE | ACKRCVE | ACKRCV | XFRDONE | FIFOEMPTY | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CSTOE | DTOE | DCRCE | RTOE | RENDE | RCRCE | RDIRE | RINDE
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TXBUFE | RXBUFF | CSRCV | SDIOWAIT | - | - | - | SDIOIRQA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ENDTX | ENDRX | NOTBUSY | DTIP | BLKE | TXRDY | RXRDY | CMDRDY

- CMDRDY: Command Ready Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is not enabled.
  1 | - | The corresponding interrupt is enabled.

- RXRDY: Receiver Ready Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is not enabled.
  1 | - | The corresponding interrupt is enabled.

- TXRDY: Transmit Ready Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is not enabled.
  1 | - | The corresponding interrupt is enabled.

- BLKE: Data Block Ended Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is not enabled.
  1 | - | The corresponding interrupt is enabled.

- DTIP: Data Transfer in Progress Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is not enabled.
  1 | - | The corresponding interrupt is enabled.

- NOTBUSY: Data Not Busy Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is not enabled.
  1 | - | The corresponding interrupt is enabled.

- ENDRX: End of Receive Buffer Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is not enabled.
  1 | - | The corresponding interrupt is enabled.

- ENDTX: End of Transmit Buffer Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is not enabled.
  1 | - | The corresponding interrupt is enabled.

- SDIOIRQA: SDIO Interrupt for Slot A Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is not enabled.
  1 | - | The corresponding interrupt is enabled.

- SDIOWAIT: SDIO Read Wait Operation Status Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is not enabled.
  1 | - | The corresponding interrupt is enabled.

- CSRCV: Completion Signal Received Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is not enabled.
  1 | - | The corresponding interrupt is enabled.

- RXBUFF: Receive Buffer Full Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is not enabled.
  1 | - | The corresponding interrupt is enabled.

- TXBUFE: Transmit Buffer Empty Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is not enabled.
  1 | - | The corresponding interrupt is enabled.

- RINDE: Response Index Error Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is not enabled.
  1 | - | The corresponding interrupt is enabled.

- RDIRE: Response Direction Error Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is not enabled.
  1 | - | The corresponding interrupt is enabled.

- RCRCE: Response CRC Error Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is not enabled.
  1 | - | The corresponding interrupt is enabled.

- RENDE: Response End Bit Error Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is not enabled.
  1 | - | The corresponding interrupt is enabled.

- RTOE: Response Time-out Error Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is not enabled.
  1 | - | The corresponding interrupt is enabled.

- DCRCE: Data CRC Error Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is not enabled.
  1 | - | The corresponding interrupt is enabled.

- DTOE: Data Time-out Error Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is not enabled.
  1 | - | The corresponding interrupt is enabled.

- CSTOE: Completion Signal Time-out Error Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is not enabled.
  1 | - | The corresponding interrupt is enabled.

- FIFOEMPTY: FIFO Empty Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is not enabled.
  1 | - | The corresponding interrupt is enabled.

- XFRDONE: Transfer Done Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is not enabled.
  1 | - | The corresponding interrupt is enabled.

- ACKRCV: Boot Operation Acknowledge Received Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is not enabled.
  1 | - | The corresponding interrupt is enabled.

- ACKRCVE: Boot Operation Acknowledge Error Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is not enabled.
  1 | - | The corresponding interrupt is enabled.

- OVRE: Overrun Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is not enabled.
  1 | - | The corresponding interrupt is enabled.

- UNRE: Underrun Interrupt Mask

  Value | Name | Description
  --- | --- | ---
  0 | - | The corresponding interrupt is not enabled.
  1 | - | The corresponding interrupt is enabled.

#### HSMCI Configuration Register

Name: HSMCI_CFG

Access: read-write

Address: 0x40000054

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | LSYNC | - | - | - | HSMODE
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | FERRCTRL | - | - | - | FIFOMODE

- FIFOMODE: HSMCI Internal FIFO control mode

-

- FERRCTRL: Flow Error flag reset control mode

  Value | Name | Description
  --- | --- | ---
  0 | - | When an underflow/overflow condition flag is set, a new Write/Read command is needed to reset the flag.
  1 | - | When an underflow/overflow condition flag is set, a read status resets the flag.

- HSMODE: High Speed Mode

  Value | Name | Description
  --- | --- | ---
  0 | - | Default bus timing mode.
  1 | - | If set to one, the host controller outputs command line and data lines on the rising edge of the card clock. The Host driver shall check the high speed support in the card registers.

- LSYNC: Synchronize on the last block

  Value | Name | Description
  --- | --- | ---
  0 | - | The pending command is sent at the end of the current data block.
  1 | - | The pending command is sent at the end of the block transfer when the transfer length is not infinite. (block count shall be different from zero)

#### HSMCI Write Protection Mode Register

Name: HSMCI_WPMR

Access: read-write

Address: 0x400000E4

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
WP_KEY
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
WP_KEY
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
WP_KEY
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | WP_EN

- WP_EN: Write Protection Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | Disables the Write Protection if WP_KEY corresponds to 0x4D4349 ("MCI' in ASCII).
  1 | - | Enables the Write Protection if WP_KEY corresponds to 0x4D4349 ("MCI' in ASCII).

- WP_KEY: Write Protection Key password

-

#### HSMCI Write Protection Status Register

Name: HSMCI_WPSR

Access: read-only

Address: 0x400000E8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
WP_VSRC
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
WP_VSRC
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | WP_VS

- WP_VS: Write Protection Violation Status

  Value | Name | Description
  --- | --- | ---
  0x0 | NONE | No Write Protection Violation occurred since the last read of this register (WP_SR)
  0x1 | WRITE | Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.)
  0x2 | RESET | Software reset had been performed while Write Protection was enabled (since the last read).
  0x3 | BOTH | Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read.

- WP_VSRC: Write Protection Violation SouRCe

-

#### HSMCI FIFO Memory Aperture0

Name: HSMCI_FIFO[0:255]

Access: read-write

Address: 0x40000200

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | -

#### HSMCI Receive Pointer Register

Name: HSMCI_RPR

Access: read-write

Address: 0x40000100

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RXPTR
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RXPTR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RXPTR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RXPTR

- RXPTR: Receive Pointer Register

-

#### HSMCI Receive Counter Register

Name: HSMCI_RCR

Access: read-write

Address: 0x40000104

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RXCTR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RXCTR

- RXCTR: Receive Counter Register

-

#### HSMCI Transmit Pointer Register

Name: HSMCI_TPR

Access: read-write

Address: 0x40000108

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TXPTR
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TXPTR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TXPTR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TXPTR

- TXPTR: Transmit Counter Register

-

#### HSMCI Transmit Counter Register

Name: HSMCI_TCR

Access: read-write

Address: 0x4000010C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TXCTR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TXCTR

- TXCTR: Transmit Counter Register

-

#### HSMCI Receive Next Pointer Register

Name: HSMCI_RNPR

Access: read-write

Address: 0x40000110

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RXNPTR
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RXNPTR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RXNPTR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RXNPTR

- RXNPTR: Receive Next Pointer

-

#### HSMCI Receive Next Counter Register

Name: HSMCI_RNCR

Access: read-write

Address: 0x40000114

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RXNCTR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RXNCTR

- RXNCTR: Receive Next Counter

-

#### HSMCI Transmit Next Pointer Register

Name: HSMCI_TNPR

Access: read-write

Address: 0x40000118

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TXNPTR
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TXNPTR
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TXNPTR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TXNPTR

- TXNPTR: Transmit Next Pointer

-

#### HSMCI Transmit Next Counter Register

Name: HSMCI_TNCR

Access: read-write

Address: 0x4000011C

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TXNCTR
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TXNCTR

- TXNCTR: Transmit Counter Next

-

#### HSMCI Transfer Control Register

Name: HSMCI_PTCR

Access: write-only

Address: 0x40000120

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | TXTDIS | TXTEN
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | RXTDIS | RXTEN

- RXTEN: Receiver Transfer Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables PDC receiver channel requests if RXTDIS is not set.

- RXTDIS: Receiver Transfer Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the PDC receiver channel requests.

- TXTEN: Transmitter Transfer Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Enables the PDC transmitter channel requests.

- TXTDIS: Transmitter Transfer Disable

  Value | Name | Description
  --- | --- | ---
  0 | - | No effect.
  1 | - | Disables the PDC transmitter channel requests.

#### HSMCI Transfer Status Register

Name: HSMCI_PTSR

Access: read-only

Address: 0x40000124

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | TXTEN
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | RXTEN

- RXTEN: Receiver Transfer Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | PDC Receiver channel requests are disabled.
  1 | - | PDC Receiver channel requests are enabled.

- TXTEN: Transmitter Transfer Enable

  Value | Name | Description
  --- | --- | ---
  0 | - | PDC Transmitter channel requests are disabled.
  1 | - | PDC Transmitter channel requests are enabled.